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Si5040
10. Serial Microcontroller Interface
Device control and status monitoring is supported with a selectable I 2 C or SPI-like interface. SPSEL (Pin 9)
controls which of the two serial formats is selected.
10.1. I 2 C Interface
When configured in I 2 C control mode (pin SPSEL tied low), the control interface to the Si5040 is a 2-wire bus for
bidirectional communication. The bus consists of a bidirectional serial data line (SD) and a serial clock input (SCK).
The SD pin may be configured as a CMOS output or as an open drain output using Register 2, bit 4. Fast mode
operation is supported for transfer rates up to 400 kbps as specified in the I 2 C-Bus Specification standard. A chip
select pin is provided (SS) to address the Si5040.
Figure 21 shows the command format for both read and write access. Data is always sent MSB first. Table 2 on
page 6 and Table 3 on page 8 give the dc and ac electrical parameters for the SCK and SD I/Os, respectively. The
timing specifications and timing diagram for the I 2 C bus can be found in the I 2 C-Bus Specification standard (fast
mode operation).
S
Slave Address
0
A Byte Address
A
Data
A
Data
A
P
Write Command
S
Slave Address
0
A
Byte Address
A
S
Slave Address
1
A
Data
A
Data A
P
Read Command
Address auto incremented after each data read or write
1 Read
From master to slave
From slave to master
0 Write
A – Acknowledge (SD LOW)
S – START condition
P – STOP condition
Figure 21. I 2 C Command Format
The device has two possible I 2 C addresses depending on the SSb pin setting. If the SSb pin is floating or externally
tied high, the device has an I 2 C address of 7d' 1000001. If the SSb pin is externally tied low, the device has an I 2 C
address of 7d' 1000000. For applications that require two Si5040 devices connected on the same I 2 C bus, each
individual device can be accessed with a unique I 2 C address depending on the SSb pin setting.
Figure 22 illustrates how the I 2 C address can be configured and what the expected value is for the first byte after
the START condition. Note that the first byte after the START condition could be either 82h or 83h depending on
whether it's a read or write. The first byte after the START condition could be either 80h or 81h depending on
whether it is a read or write.
By design, this bit in the I 2 C address
is determined by the SSb pin.
Per I 2 C specification, this bit is
either 1 for read or 0 for write.
1
0
0
0
0
0
X
Source: Fig 14 of I 2 C – Bus Specification Version 2.1
Figure 22. Device I 2 C Address
Rev. 1.3
35
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